Process method and structure for high voltage mosfets

ABSTRACT

This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches formed at a top portion of the semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction each having a nonlinear portion comprising a sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the perpendicular sidewall wherein the sidewall dopant region extends vertically downward along the perpendicular sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

CROSS REFERENCE TO OTHER APPLICATIONS

This application is a Divisional Application of application Ser. No.15/396,384 filed on Dec. 30, 2016, application Ser. No. 15/396,384 is aDivisional Application of application Ser. No. 14/011,078 filed on Aug.27, 2013 that is now issued into U.S. Pat. No. 9,755,052 on Sep. 5,2017. Application Ser. No. 14/011,078 is a Continuation-In-Part (CIP) ofand claims priority to U.S. patent application Ser. No. 13/892,191entitled “A PROCESS METHOD AND STRUCTURE FOR HIGHVOLTAGE MOSFETS,” filedMay 10, 2013, and issued into U.S. Pat. No. 9,887,283 on Feb. 6, 2018.The disclosures made in application Ser. Nos. 13/892,191, 14/011,078,and 15/396,384 are incorporated herein by reference for all purposes.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The invention relates generally to the manufacturing processes andstructures of semiconductor power devices. More particularly, thisinvention relates to simplified manufacturing processes and structuralconfigurations of improved high voltage (HV) metal oxide semiconductorfield effect transistors (MOSFET).

2. Description of the Prior Art

Conventional methods of manufacturing high voltage (HV) MOSFET devicesare encountered with difficulties and limitations to further improve theperformances due to different tradeoffs. In the vertical semiconductorpower devices, there is a tradeoff between the drain to sourceresistance, i.e., on-state resistance, commonly represented by RdsA,i.e., Rds X Active Area, as a performance characteristic, and thebreakdown voltage sustainable of the power device. Several deviceconfigurations have been explored in order to resolve the difficultiesand limitations caused by these performance tradeoffs. SpecialP-composition (PCOM) structures are developed particularly to achievethese purposes. Specifically, the high voltage (HV) MOSFET devicesimplemented with the PCOM configurations include P-type dopant regionssurrounding the sidewalls of the shielding trenches to link between theP-type body region formed at the top surface of the semiconductorsubstrate and a P-type dopant region below the shielding trenches. Inorder to form the sidewall dopant regions surrounding the trenchsidewalls, the conventional methods apply an additional implanting maskwith implanting openings to carry out the implantation processes on thetrench sidewalls at the selected locations of the shielding trenches.Furthermore, in order to assure the dopant ions are implanted into thebottom portions of the trench sidewalls, implantations of dopant ions athigh energy must be applied. The requirements of additional mask and theprocesses of applying high energy dopant ions cause the increase of themanufacturing costs. Additionally, high energy implantations into thebottom portions of the trench sidewalls followed with a diffusionprocess generally have less control of the formation of the dopantregions. These uncertainties of the manufacturing processes result ingreater variations of device performance and less accurate control ofthe manufacturing qualities.

FIG. 1A is a top view of an implanting mask 100 used in the conventionalprocess and FIGS. 1B and 1C are two cross sectional views illustratingthe configurations of a high voltage (HV) MOSFET device formed byapplying conventional process along lines 1-1′ and 2-2′ of FIG. 1Acorrespondingly. As shown in FIG. 1A, the implanting openings 11 arelocated on the selected regions of the trenches 12. In order to form aMOSFET device that can sustain high power operations, a PCOM(P-composition) configuration is formed. In this PCOM MOSFET structure,special dopant regions are formed in part of the areas 16 below theP-type body region 13 through the implanting openings 11 to link theP-type body region and a P-type dopant region 15 below the trench 12 asshown in FIG. 1C. Meanwhile, in other areas, the implantation formingthe dopant regions below the body regions is blocked by the implantingmask 100. The implant mask shown in FIG. 1A blocks the dopant implantedthrough the sidewalls of the trench in areas around 1-1′. FIG. 1B showsa configuration where there are no dopant regions surrounding the trenchsidewalls to link the body regions and the dopant regions below thetrench bottom. As shown in FIGS. 1B-1C, the high voltage (HV) MOSFETdevice also includes a planar gate 17 formed atop the semiconductorsubstrate and a source 18 and a P++ contact 19 formed at a top portionof the P-type body region 13.

The conventional manufacturing processes as shown in FIGS. 1A to 1Crequires an additional implanting mask. Furthermore, a high energyimplant of P-type dopant, e.g., P-type dopant implant in the Mev ranges,is required to form the dopant regions below the body regionssurrounding the trench sidewalls shown in FIG. 1C. The manufacturingcosts are increased due to the additional mask and high energy implantrequirements.

Therefore, a need still exists for the ordinary skill in the art toimprove the methods of manufacturing of the power devices, particularlythe devices with the PCOM configuration to resolve these technicallimitations. It is the purpose of this invention to provide new andimproved methods of manufacturing and device configurations to eliminatethe requirements of additional implanting mask and high energyimplantations such that the above-discussed difficulties and limitationscan be overcome.

SUMMARY OF THE PRESENT INVENTION

It is therefore an aspect of the present invention to provide a new andimproved method of manufacturing for implanting the trench sidewallP-type dopant regions without requiring an additional implanting maskand without requiring a high energy dopant implant such that the cost ofmanufacturing can be reduced, whereby the above discussed limitationsand difficulties can be resolved.

Specifically, it is an aspect of this invention that the implantingprocess takes advantage of the special configuration of the sidewalls atthe trench endpoints where the sidewall perpendicular to thelongitudinal direction of the trench is inherently exposed to open spaceas part of the trenches. Therefore, a P-type dopant region implantedthrough this endpoint sidewall can be carried out to reach the bottomP-type dopant region formed at the bottom of the trench withoutrequiring the application of high energy dopant ions because the dopantions are projected only through open space of the trenches withoutrequiring penetrating through the semiconductor substrate. The PCOMdopant regions linking the P-type body regions formed at the top surfaceof the semiconductor substrate and the trench bottom P-type dopantregions are therefore formed only at the sidewalls of the trenchendpoint. In contrast to the conventional methods, cost savings areachieved without requiring a high energy dopant implant.

In addition, it is an aspect of this invention that the implantingprocess takes advantage of the special configuration of the trenchsidewalls at the trench bends where the sidewall perpendicular to thelongitudinal direction of the trench is inherently exposed to open spaceas part of the trenches. Furthermore, it is an aspect of this inventionthat the implanting process takes advantage of the special configurationof the trench sidewalls at the trench notches where the sidewallperpendicular to the longitudinal direction of the trench is inherentlyexposed to open space as part of the trenches. Therefore, a P-typedopant region implanted through this sidewall can be carried out toreach the bottom P-type dopant region formed at the bottom of the trenchwithout requiring the application of high energy dopant ions because thedopant ions are projected only through open space of the trencheswithout requiring penetrating through the semiconductor substrate.

It is another aspect of this invention that the sidewall dopant implantthrough the open space along the longitudinal direction of the trenchonto a trench sidewall at the trench endpoint, trench bend and trenchnotch provides better control over the implanting process. The deviceperformance parameters are more accurately controllable andmanufacturing variations caused by uncertainties due to high energydopant implant to penetrate through substrate are reduced.

In a preferred embodiment, this invention discloses a semiconductorpower device disposed in a semiconductor substrate. The semiconductorpower device comprises a plurality of shielding trenches formed at thetop portion of the semiconductor substrate each having a trench endpointwith an endpoint sidewall perpendicular to a longitudinal direction ofthe trench and extends vertically downward from a top surface to atrench bottom surface. The semiconductor power device further includes atrench bottom P-type dopant region disposed below the trench bottomsurface and a sidewall P-type dopant region disposed along the endpointsidewall wherein the sidewall P-type dopant region extends verticallydownward along the endpoint sidewall of the trench to reach the trenchbottom P-type dopant region and connect the trench bottom P-type dopantregion to a P-type body region formed at the top surface of thesemiconductor substrate.

In another preferred embodiment, this invention discloses asemiconductor power device disposed in a semiconductor substrate. Thesemiconductor power device comprises a plurality of shielding trenchesformed at the top portion of the semiconductor substrate each having aplurality of small bends in predesigned areas with trench sidewallsperpendicular to a longitudinal direction of the trench and extendsvertically downward from a top surface to a trench bottom surface. Thesemiconductor power device further includes a trench bottom P-typedopant region disposed below the trench bottom surface and a sidewallP-type dopant region disposed along the bend sidewall wherein thesidewall P-type dopant region extends vertically downward along the bendsidewall of the trench to reach the trench bottom P-type dopant regionand connect the trench bottom P-type dopant region to a P-type bodyregion formed at the top surface of the semiconductor substrate.

In another preferred embodiment, this invention discloses asemiconductor power device disposed in a semiconductor substrate. Thesemiconductor power device comprises a plurality of shielding trenchesformed at the top portion of the semiconductor substrate each having aplurality of small notches in predesigned areas with trench sidewallsperpendicular to a longitudinal direction of the trench and extendsvertically downward from a top surface to a trench bottom surface. Thesemiconductor power device further includes a trench bottom P-typedopant region disposed below the trench bottom surface and a sidewallP-type dopant region disposed along the notch sidewall wherein thesidewall P-type dopant region extends vertically downward along thenotch sidewall of the trench to reach the trench bottom P-type dopantregion and connect the trench bottom P-type dopant region to a P-typebody region formed at the top surface of the semiconductor substrate.

In a preferred embodiment, this invention further discloses a method formanufacturing a semiconductor power device on a semiconductor substrate.The method includes a step of a) applying a hard oxide mask atop asemiconductor substrate followed by patterning the hard oxide maskaccording to a pre-determined trench configuration; b) etching throughthe patterned hard mask to form a plurality of trenches at the topportion of the semiconductor substrate each having a trench endpoint, asmall bend or a small notch with a sidewall perpendicular to alongitudinal direction of the trench and vertically extending downwardfrom a top surface to a trench bottom surface; c) applying a vertical(zero degrees) high energy implant to form trench bottom P-type dopantregions below the trench bottom surface followed by removing the hardmask; d) growing an oxide liner atop the silicon surface at the sidewalland bottom of the trenches; and e) applying a low energy tilt implantwherein dopant ions are implanted along a designated tilt angle to forma sidewall P-type dopant region along the perpendicular sidewall, wherethe sidewall P-type dopant region extends vertically downward along thesidewall of the trench to reach the trench bottom P-type dopant regionand connect the trench bottom P-type dopant region to a P-type bodyregion formed at the top surface of the semiconductor substrate. In oneof the embodiments, the dopant ions are implanted along a tilt angleapproximately 45 degrees relative to the sidewall surfaces.

These and other objects and advantages of the present invention will nodoubt become obvious to those of ordinary skill in the art after havingread the following detailed description of the preferred embodiment,which is illustrated in the various drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a top view of an implanting mask used in conventional processand FIGS. 1B and 1C are two side cross-sectional views of the PCOMPconfigurations along two different locations across the trenchcorresponding to those shown on the implanting mask 100 of FIG. 1A.

FIG. 2A is a top view of a conventional trench configuration on asemiconductor substrate.

FIGS. 2B, 2C-1, 2C-2, 2D-1, 2D-2, 2E-1, 2E-2 are side cross sectionalviews showing some steps of the process to form a PCOMP configuration attwo different locations of the trench of the present invention.

FIGS. 2F-1 and 2F-2 are side cross sectional views showing analternative embodiment of FIGS. 2B-1 and 2B-2.

FIGS. 2G-1, 2G-2, 2H-1 and 2H-2 are side cross sectional views showinganother alternative embodiment of FIGS. 2E-1 and 2E-2.

FIG. 3A is a top view of an alternate configuration of trenches ofvarious lengths on a semiconductor substrate of the present invention.

FIG. 3B is a top view of the semiconductor substrate of FIG. 3A afterthe vertical and tilt implantations to form a PCOMP configuration.

FIG. 4A is a top view of an alternate configuration of trenches on asemiconductor substrate where the trench has a nonlinear portioncomprising small bends according to an embodiment of this invention.

FIG. 4B is a top view of the semiconductor substrate of FIG. 4B afterthe vertical and tilt implantations to form a PCOMP configuration.

FIG. 5A is a top view of another alternate configuration of trenches ona semiconductor substrate where the trench has a nonlinear portioncomprising small notches according to an embodiment of this invention.

FIG. 5B is a top view of the semiconductor substrate of FIG. 5A afterthe vertical and tilt implantations to form a PCOMP configuration.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2A is a top view of a conventional trench configuration on asemiconductor substrate. FIGS. 2B, 2C-1, 2C-2, 2D-1, 2D-2, 2E-1, 2E-2,2F-1, 2F-2, 2G-1, 2G-2, 2H-1 and 2H-2 are side cross sectional viewsillustrating the processing steps of forming the PCOM structuralconfiguration along the line 1-1′ and line 2-2′ in FIG. 2A respectivelyin different embodiments of the present invention.

As shown in FIG. 2A, a plurality of trenches 120 are formed on asemiconductor substrate 101 with each trench 120 having a trenchendpoint sidewall 110. The plurality of trenches 120 can be formed asfollow: an oxide hard mask 111 is deposited atop the semiconductorsubstrate as shown in FIG. 2B; then the hard mask 111 is patternedaccording to a pre-determined configuration similar as the that shown inFIG. 2A; and the semiconductor substrate 101 is then anisotropicallyetched out through the patterned hard mask 111 to form the a pluralityof trenches 120 with each trench 120 having trench endpoints 110 asshown in FIGS. 2C-1 and 2C-2.

A vertical high energy P-type dopant implantation (zero degrees) isfirst carried out, through the patterned hard mask 111, to form theP-type dopant regions 130 below the bottom surface of the trench 120 asshown in FIGS. 2D-1 and 2D-2. The P-type dopant regions 130 function asRESURF at trench bottom for providing a maximum BV (break down voltage)blocking capability.

As shown in FIGS. 2E-1 and 2E-2, the hard mask 111 is removed and then athin oxide layer 115 is deposited on the top surface of the substrate101, on the sidewalls and the bottom surface of the trench 120 and atthe endpoint sidewall 110 with a same thickness shown as t. Then a lowenergy tilt P-type dopant implantation, for example at 45 degrees, iscarried out. In FIG. 2E-1, the P-type dopant regions 140 are formed atthe top surface of the substrate, below the bottom surface of the trench120 and only at the top portions surrounding the trench sidewalls. InFIG. 2E-2, the tilt implantation is also carried out at the endpointsidewall 110 at the endpoints of the trenches 120, thus the P-typedopant regions 140 are now formed along the entire length of the trenchendpoint sidewalls 110, below the bottom surface of the trench 120 andat the top surface of the substrate 101. The PCOMP structuralconfigurations is achieved with the P-type dopant regions 140 formedalong the entire length of the trench endpoint sidewalls 110 that linkthe P-body regions (not shown) to the bottom P-type dopant regions 130without requiring additional implant mask and without requiring a highenergy implantation. The manufacturing process proceeds with standardprocessing steps to complete the devices.

In FIGS. 2E-1 and 2E-2, as described above, a thin oxide layer 115 witha uniform thickness t is deposited on the top surface of the substrate101 and on the sidewalls and the bottom surface of the trenches 120 andthe endpoint sidewall 110. FIGS. 2F-1 and 2F-2 are side cross sectionalviews similar to that of FIGS. 2E-1 and 2E-2. In this embodiment, theoxide layer 125′ deposited at the top surface of the substrate 101 andat the bottom surface of the trench 120 has a thickness t2 greater thanthe thickness t1 of the oxide layer 125 covering the sidewalls of thetrench 120 and the trench endpoint sidewall 110. The thickness t2 of theoxide layer 125′ is thick enough to block the implantation at the topsurface of the substrate 101 and below the bottom surface of the trench120. As a result, after the low energy tilt angle implantation iscarried out, as shown in FIG. 2F-1, the P-type dopant regions 140 areonly formed at the top portions surrounding the sidewalls of thetrenches 120. In FIG. 2F-2, the P dopant regions 140 are only formedalong the entire length of the trench endpoint sidewalls 110. As such,the PCOMP structural configurations is achieved with the dopant regions140 formed along the entire length of the trench endpoint sidewalls 110that links the P-type body regions formed at the top surface of thesemiconductor substrate (not shown) to the bottom P-type dopant regions130 without requiring an additional implant mask and without requiring ahigh energy implantation. The manufacturing process proceeds withstandard processing steps to complete the devices.

In an alternative embodiment, if a thin oxide layer 115 with a uniformthickness t is deposited on the top surface of the substrate 101 and onthe sidewalls and the bottom surface of the trenches 120 and theendpoint sidewall 110 similar to that shown in FIGS. 2E-1 and 2E-2, toprevent the tilted implantation punching through the oxide layer at thebottom of the trench 120, before the tilted implantation is carried out,a layer of sacrificial materials 142 is deposited at the bottom of thetrench 120 in certain controlled thickness as shown in FIGS. 2G-1 and2G-2. The layer 142 can be high-density plasma (HDP) oxide photoresist,TEOS and the likes. As a result, after the low energy tilt angleimplantation is carried out, as shown in FIG. 2G-1, the P-type dopantregions 140 are only formed at the top portions surrounding thesidewalls of the trenches 120 and at the top surface of thesemiconductor substrate 101, and in FIG. 2G-2, the P dopant regions 140are only formed along the entire length of the trench endpoint sidewalls110 and at the top surface of the semiconductor substrate 101. Thesacrificial material layer 142 is then removed as shown in FIGS. 2H-1and 2H-2 before the trench 120 is filled with polysilicon in a nextprocessing step. The manufacturing process proceeds with standardprocessing steps to complete the devices.

FIGS. 3A-3B show an alternative embodiment of the present invention. Asshown in FIG. 3A, which is a top view of an alternate trenchconfiguration on a semiconductor substrate 101 of the present invention,the length of the trenches 120′ are adjusted by providing trenchendpoints at predesigned areas, for example the length of trenches 120′is shorter than that of trenches 120 shown in FIG. 2A, thus the densityof the trench endpoint sidewalls 110′ and so as the density of the PCOMPstructural configurations is adjusted, thus the PCOMP structuralconfigurations with the P-type dopant regions formed along the entirelength of the trench endpoint sidewalls that links between the P-typebody regions formed at the top surface of the semiconductor substrate tothe trench bottom P-type dopant regions are distributed over entire areaof the semiconductor substrate. FIG. 3B is a top view of thesemiconductor substrate 101 after the implantation is carried out usingthe implantation processes described above forming PCOMP structuralconfigurations. As shown in FIG. 3B, the vertical implantation of theP-type dopant through the trench hard mask forms the P-type dopantregions 130 below the bottom surface of the trench 120′ and the tiltangle P-type dopant implantation at the trench endpoint sidewalls 110′forms the P-type dopant regions 140 along the entire length of thetrench endpoint sidewalls 110′. Depending on the space between twoendpoints of two adjacent trenches 120′, the P-type dopant regions 140can be merged together, as shown in FIG. 3B, or can be separated fromeach other (not shown).

FIGS. 4A-4B show an alternative embodiment of the present invention. Asshown in FIG. 4A, which is a top view of an alternate trenchconfiguration on a semiconductor substrate 101 of the present invention,each trench 200 has a nonlinear portion comprising small bends 210 atpredesigned areas, thus forming trench sidewalls 220 oriented along adirection nonlinear with the trench longitudinal direction. In the bends210 shown in FIG. 4A, the trench sidewalls 220 are perpendicular to thelongitudinal direction of the trench 200. Therefore, the entire verticallength of the sidewall 220 is exposed to dopant ions projected along atrench longitudinal direction with a tilted angle in a tilted ionimplant. Therefore, the tilted ion implant may be performed with lowenergy dopant ions to reach the bottom of the trench sidewalls 220 sincethe entire vertical length of the trench sidewalls is exposed. FIG. 4Bis a top view of the semiconductor substrate 101 after the implantationis carried out using the implantation processes described above formingPCOMP structural configurations. As shown in FIG. 4B, the verticalimplantation of the P-type dopant through the trench hard mask forms theP-type dopant regions 130 below the bottom surface of the trench 200 andthe tilt angle P-type dopant implantation at the trench sidewalls 220 ofthe bends 210 and the trench endpoint sidewalls 110 forms the P-typedopant regions 140 along the entire length of the trench sidewalls 220and the endpoint sidewalls 110.

FIGS. 5A-5B show an alternative embodiment of the present invention. Asshown in FIG. 5A, which is a top view of an alternate trenchconfiguration on a semiconductor substrate 101 of the present invention,each trench 250 has a nonlinear portion comprising small notches 260 atpredesigned areas, thus forming trench sidewalls 270 oriented along adirection nonlinear with the trench longitudinal direction. In thenotches 260 shown in FIG. 5A, the trench sidewalls 270 are perpendicularto the longitudinal direction of the trench 250. Therefore, the entirevertical length of the sidewall 270 is exposed to dopant ions projectedalong a trench longitudinal direction with a tilted angle in a tiltedion implant. Therefore, the tilted ion implant may be performed with lowenergy dopant ions to reach the bottom of the trench sidewalls 270 sincethe entire vertical length of the trench sidewalls is exposed. FIG. 5Bis a top view of the semiconductor substrate 101 after the implantationis carried out using the implantation processes described above formingPCOMP structural configurations. As shown in FIG. 5B, the verticalimplantation of the P-type dopant through the trench hard mask forms theP-type dopant regions 130 below the bottom surface of the trench 250 andthe tilt angle P-type dopant implantation at the trench sidewalls 270 ofthe notches 260 and the trench endpoint sidewalls 110 forms the P-typedopant regions 140 along the entire length of the trench sidewalls 220and the endpoint sidewalls 110.

In general, the alternate trench configuration as shown in FIGS. 4A, 4B,and 5A, 5B can be further implemented by forming the trenches tocomprise a portion at specific areas with either shrunken or enlargedwidths. The portion of trenches in these areas thus forming trenchsidewall oriented along a direction perpendicular to the longitudinaldirection of the trench thus exposing an entire vertical length of thesidewalls to allow implanting ions to penetrate to entire vertical depthof the sidewalls without requiring a high energy ion implantation informing the PCOMP structural configurations. Furthermore, the alternatetrench configuration may also be implemented by forming the trencheswith a lateral bending configuration thus exposing trench sidewallsavailable for full vertical depth implantation in forming the PCOMPstructural configurations without requiring a high energy ionimplantation.

Although the present invention has been described in terms of thepresently preferred embodiment, it is to be understood that suchdisclosure is not to be interpreted as limiting. Various alterations andmodifications will no doubt become apparent to those skilled in the artafter reading the above disclosure. Accordingly, it is intended that theappended claims be interpreted as covering all alterations andmodifications as fall within the true spirit and scope of the invention.

I claim:
 1. A semiconductor power device disposed in a semiconductorsubstrate comprising: a trench formed at a top portion of thesemiconductor substrate extending laterally across the semiconductorsubstrate along a longitudinal direction wherein the trench furthercomprises a laterally notch having a laterally notch trench sidewalloriented along a nonlinear direction relative to the longitudinaldirection to expose an entire vertical length of the trench sidewallfacing the longitudinal direction to receive directly dopant ionsprojected by a tilted implant along the longitudinal direction to form afull-length sidewall dopant region along the entire vertical length ofthe notch trench sidewall; and a trench bottom dopant region disposedbelow the trench bottom surface and an upper partial sidewall dopantregion disposed on an upper portion of the trench sidewalls along thelongitudinal direction wherein the full-length sidewall dopant regiondisposed along the notch trench sidewall extends vertically downwardalong the intersecting sidewall in the nonlinear portion of the trenchto reach the trench bottom dopant region to pick-up the trench bottomdopant region to the top surface of the semiconductor substrate.
 2. Thesemiconductor power device of claim 1 wherein: the laterally notchtrench sidewall extends along a perpendicular direction relative to thelongitudinal direction.
 3. The semiconductor power device of claim 1wherein: the trench is padded with an insulation layer coveringsidewalls and the trench bottom surface.
 4. The semiconductor powerdevice of claim 1 wherein: the trench is padded with an insulation layercovering sidewalls and the trench bottom surface wherein the insulationlayer covers the sidewalls and the trench bottom surface havingapproximately a same thickness.
 5. The semiconductor power device ofclaim 1 wherein: the trench is padded with an insulation layer coveringsidewalls and the trench bottom surface wherein the insulation layercovering the sidewalls having a smaller layer thickness than theinsulation layer covering the trench bottom surface.
 6. Thesemiconductor power device of claim 1 wherein: the trench is configuredto have the laterally notch trench sidewall distributed at designatedlocations on the entire area of the semiconductor substrate.
 7. Thesemiconductor power device of claim 1 further comprising: a high voltage(HV) MOSFET device.
 8. The semiconductor power device of claim 1 furthercomprising: a high voltage (HV) IGBT device.
 9. The semiconductor powerdevice of claim 1 wherein: at least one of the trenches having at leasttwo laterally notch trench sidewalls.